1. Field of the Invention
The present invention relates to an input/output control system and methods for controlling a series of control words of an input/output program to control the operations of peripheral equipment of an information processor.
2. Prior Art
Hardware for controlling data transfer between an input/output device and a memory is generally called a channel. A conventional channel services a single input/output device at a time. It is very inefficient, however, for a channel with a high transfer rate of several hundred thousand characters per second is exclusively used by an input/output device with a low data transfer rate, at most one thousand characters per second, such as a paper tape reader.
There is one approach to solve the inefficient use in which a plurality of channels with a low transfer rate are used. This approach, however is not preferable in that the amount of hardware used is increased, the control is complicated to that extent, and the manufacturing cost also is high.
Another approach proposed is to use a channel with a high data transfer rate commonly with a plurality of input/output devices in time-division multiplexing mode.
In such a system, the input/output device specifies a memory address for data storing and an index (I/O device number, channel number) of another device to which data is to be transferred.
In an ordinary channel, the I/O device number of an I/O device for storing data is specified by an element for the channel such as an internal counter provided in an arithmetic and logic unit or a control word. With such an arrangement, a program is used for the data transfer to and from a plurality of input/output devices.
In the above-mentioned system, the input/output operation may be performed by hardware, not by software, in the following manner. As input/output device transfers the index to the channel. The address in a main memory specified by the index is read out. That address stores the address in which the next incoming data is stored. The address read out from the main memory unit (MMU) is set in an address selector and the address is incremented or decremented and then is loaded into the corresponding address of the main memory unit. The data succeedingly transferred is stored in the address of the memory in accordance with the contents of the address selector. In this mode, if indexes are differently assigned to the input/output devices respectively, data may be stored in a desired input/output device.
The data transfer control system with one channel for the plurality of input/output devices is advantageous in that it can effectively achieve data transfer since a high speed channel is not occupied by a plurality of input/output devices with low transfer rate. For this reason, the control system is useful for a communication control system.
In the channel of the above-mentioned type, the input/output instruction is executed in a central processing unit (CPU) so that the data transfer is started between the input/output device and the channel specified by the instruction. After the data transfer is once started, the succeeding control of the data transfer is performed independently of the CPU, and the channel performs the input/output operation. Thus, the channel is independent of the CPU. A series of input/output operations are performed under control of an input/output program consisting of a plurality of input/output commands. The input/output commands included in the channel program are for data transfer, transfer of the auxiliary control information to the input/output device, reading out the status information from the input/output device and the like.
The channel, which is responsive to the instruction in the "main program" fetched and executed by the CPU, fetches and executes a "channel program". The channel program consists of a plurality of instructions called channel command words (CCW). In order to execute various operations for a single input/output device in a predetermined sequence, the CCWs corresponding to the various operations are chained to one another. The CCWs represent the kinds of channels, the addresses of the memory where data to be transferred is stored, the number of bytes of data to be transferred, etc. The write and read operations to and from the addresses of the main memory serving as a storage for the information are carried out by chaining the CCWs to one another.
In this case channel command is specified by the first CCW and the memory locations where data is to be transferred is specified by the subsequent CCWs. The CCWs, together with other parameters, form a channel control block (CCB). The CCB is provided for each input/output device and each channel. The address table of the CCB is provided in a given system area of the memory. A start I/O instruction ( SIO instruction) is executed by the CPU, with parameters of the channel number and the I/O unit number so that a given CCB address is obtained from the given channel number and the I/O device number. A given CCB is read out from the address and its contents is set in the channel. Subsequently, the channel controls the input/output device on the basis of the information given so that data is transferred.
In the scheme thus far mentioned, however, the address of the CCB must be set in a predetermined system area of the MMU and this is defective to the effective utilization of the memory. The work to retrieve the CCB address table and the CCB address must be carried out in relation with the CPU and thus this deteriorates the CPU utilization.